TXLVL=DISABLED, TXERR=DISABLED, RXLVL=DISABLED, RXERR=DISABLED
FIFO interrupt enable set (enable) and read register.
| TXERR | Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. 0 (DISABLED): No interrupt will be generated for a transmit error. 1 (ENABLED): An interrupt will be generated when a transmit error occurs. |
| RXERR | Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. 0 (DISABLED): No interrupt will be generated for a receive error. 1 (ENABLED): An interrupt will be generated when a receive error occurs. |
| TXLVL | Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 0 (DISABLED): No interrupt will be generated based on the TX FIFO level. 1 (ENABLED): If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. |
| RXLVL | Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. 0 (DISABLED): No interrupt will be generated based on the RX FIFO level. 1 (ENABLED): If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. |